Volume 4 Issue 1 January-March 2016
OPTIMIZED MAXIMUM POWER POINT TRACKING(MPPT) OF A SOLAR PV SYSTEM WITH IMPROVED P&O METHOD [pp 07-11]
Manohar Murli, Sengar Ran vijay Singh
Abstract— As the power demand increasing day by day, the power failure is also increasing. So, the renewable energy can be used to provide constant loads. To convert the basic circuit equation of solar cell into simplified form, a model is developed including the effects of changing solar irradiation and temperature. Maximum power point tracker (MPPT) control is essential to ensure the output of photovoltaic power generation system at the maximum power output as possible. Maximum power point tracking (MPPT) techniques are used in PV systems to make maximum utilization of PV array output power which depends on solar irradiation ….
INTELLIGENT CONTROL AND DYNAMIC PERFORMANCE ENHANCEMENT USING UPFC [pp 12-14]
Singh Reena, Bondriya Pallavi
Abstract –Due to the increasing demand of electricity the quantity of nonlinear load also get increased. Hence due to the increase in non-linear load it is being difficult to maintain the stability and security of the power system. In order to overcome from this difficulty a new approach fuzzy logic with UPFC is used in this paper. This intelligent control system is applied which enhances the transmission system. Fuzzy system uses the membership function ….
ANALYSIS AND COMPARISON OF VARIOUS FACTS DEVICES [pp 15-17]
Singh Reena, Bondriya Pallavi, Kushwaha Mitali
Abstract – This paper provides various applications and comparison of facts devices. Facts devices are basically used in transmission lines to regulate the reactive power balance in the transmission network. Facts devices can be classified on the basis of their control strategy either as series or shunt compensators. In this paper a brief description about various facts devices….
A FAST BINARY TO BCD CONVERSION FOR B/D MULTIOPERAND ADDER [pp 18-22]
Tiwari Shikha, Srivastava Hari Shanker
Abstract – This paper design a new architecture for a 8 bit Binary to BCD (BD) converter which forms the core of our Proposed high speed high performance and low power decimal Multi-operand Adder. It is intend to design that contains various improvements ended existing architectures. These include an improved BD Converter that helps in reducing the delay reducing area of the Multi-operand decimal Adder. Simulation results indicate that with a insignificant reduce in area, the proposed BD converter reveals an improvement of m